`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/09/15 14:22:04
// Design Name: 
// Module Name: DM
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module DM(
    input   wire        clk,
    input   wire        rst,

    input   wire [31:0] i_addr,
    input   wire [31:0] i_wr_data,
    input   wire        i_wr_en,
    
    output  wire [31:0] o_data
    );
    
    reg [7:0] mem [255:0];
    
    wire [7:0] _addr;
    assign _addr = i_addr[7:0];
    
    reg [31:0] t_data;
    assign o_data = t_data;
    
    always @(posedge clk) begin
        if (i_wr_en == 1) begin
            mem[_addr] <= i_wr_data[7:0];
            mem[_addr + 1] <= i_wr_data[15:8];
            mem[_addr + 2] <= i_wr_data[23:16];
            mem[_addr + 3] <= i_wr_data[31:24];
        end else begin
            t_data =
                {mem[_addr + 3], mem[_addr + 2], mem[_addr + 1], mem[_addr]};
        end
    end
    
endmodule
